The present invention relates to semiconductor design technology, and more particularly, to a delay locked loop circuit of a semiconductor memory device.
In general, input/output data should be timely synchronized with a reference clock in a synchronous semiconductor memory device such as a double data rate synchronous dynamic random access memory device (DDR SDRAM).
Herein, since the reference clock mainly represents an external clock CLK, CLKB inputted from an external device such as a memory controller, in order to transmit data that is timely synchronized with the reference clock, a point in time where the data transmitted from the synchronous semiconductor memory device is outputted and an edge or a center of the external clock CLK, CLKB should be exactly in accord with each other.
However, as can be seen from an example of an asynchronous semiconductor memory device, although a command for outputting data and the external clock CLK, CLKB are inputted to a general semiconductor memory device, data that is timely synchronized with the external clock CLK, CLKB is not automatically outputted.
The reason why the data is not synchronized with the external clock CLK, CLKB in the semiconductor memory device is as follows.
First of all, if the external clock CLK, CLKB that is buffered into the semiconductor memory device through an input buffering circuit is called an internal clock, a phase of the internal clock is changed as the internal clock passes through all internal circuits included in the semiconductor memory device such as control circuits, peripheral circuits, a cell array and so on. Therefore, the internal clock is not timely synchronized with the external clock CLK, CLKB when the internal clock arrives at an output buffering circuit and is outputted to the external.
At this time, since the data is outputted from the semiconductor memory device by being synchronized with the internal clock, the data outputted from the semiconductor memory device is not synchronized with the external clock CLK, CLKB due to a phase difference between the internal clock and the external clock CLK, CLKB.
Therefore, in order to output data being timely synchronized with a phase of the external clock CLK, CLKB that is a standard in the semiconductor memory device, a time, by which the internal clock is delayed until the external clock CLK, CLKB inputted as the internal clock is transferred to an output pad should be conversely compensated to the internal clock coupled to the output pad to make the phase of the internal clock being synchronized with the phase of the external clock CLK, CLKB.
As described above, a representative circuit that performs a function of synchronizing the phase of the internal clock with the phase of the external clock CLK, CLKB by conversely compensating the time by which the phase of the internal clock is delayed is a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit.
The PLL circuit is a device mainly used to simultaneously synchronize a frequency and a phase using a frequency multiplication function in case that a frequency of the internal clock used within the semiconductor memory device becomes different from a frequency of the external clock inputted from the external as a standard.
Meanwhile, the DLL circuit is a device used to synchronize only a frequency in case that the frequency of the internal clock is the same as that of the external clock.
Like this, since the PLL circuit has an additional function such as the frequency multiplication function compared to the DLL circuit when comparing only features of the PLL circuit and the DLL circuit, the PLL circuit is supposed to be used more often than the DLL circuit. However, the DLL circuit is practically used more often than the PLL circuit in case of the semiconductor memory device.
There are various reasons therefor. The representative reason is that the DLL circuit is stronger than the PLL circuit against noise and the DLL circuit requires a much smaller area than the PLL circuit.
FIG. 1 illustrates a block diagram of a DLL circuit in a conventional semiconductor memory device.
Referring to FIG. 1, the conventional DLL circuit includes a delay locking block 100, a phase detecting block 120 and a phase mixing block 140.
The delay locking block 100 generates a first delay clock RISING_CLK corresponding to a first clock edge of a source clock REF_CLK and a second delay clock FALLING_CLK corresponding to a second clock edge of the source clock REF_CLK to achieve the delay locking.
The phase detecting block 120 outputs a weight selection signal WR_SEL by detecting a phase difference between the first delay clock RISING_CLK and the second delay clock FALLING_CLK.
The phase mixing block 140 outputs delay locked loop clocks DLL_CLK_USE and DLL_CLK_DUMMY by reflecting a weight corresponding to the weight selection signal WR_SEL to the first delay clock RISING_CLK and the second delay clock FALLING_CLK at a point in time where the first delay clock RISING_CLK and the second delay clock FALLING_CLK are delay-locked and mixing phases of the first delay clock RISING_CLK and the second delay clock FALLING_CLK.
The conventional DLL circuit further includes a phase split block 110A for generating first and second phase split clocks RCLKDLL and FCLKDLL by splitting phases of the delay locked loop clocks DLL_CLK_USE and DLL_CLK_DUMMY and a dummy phase split block 110B that has the same construction as that of the phase split block 110A but does not operate practically.
The phase mixing block 140 includes a delay locking enable signal generating sector 146, a mixing control sector 142, a duty cycle correction (DCC) phase mixing sector 144 and a dummy DCC phase mixing sector 145.
The delay locking enable signal generating sector 146 generates a delay locking enable signal DCC_EN whose logic level is determined in response to a first delay locking signal LOCK_STATE_R corresponding to whether the first delay clock RISING_CLK is delay-locked or not and a second delay locking signal LOCK_STATE_F corresponding to whether the second delay clock FALLING_CLK is delay-locked.
The mixing control sector 142 generates a mixing control signal CTRL to control a mixing ratio of the first delay clock RISING_CLK and the second delay clock FALLING_CLK in response to the weight selection signal WR_SEL when the delay locking enable signal DCC_EN is enabled.
The DCC phase mixing sector 144 outputs the delay locked loop clock DLL_CLK_USE by mixing the phases of the first delay clock RISING_CLK and the second delay clock FALLING_CLK in the mixing ratio corresponding to the mixing control signal CTRL.
The dummy DCC phase mixing sector 145 has the same construction as that of the DCC phase mixing sector 144 but does not operate practically.
The delay locking block 100 includes a first phase delay sector 102, a second phase delay sector 104, a first delay duplication modeling sector 103 and a second delay duplication modeling sector 105. Furthermore, the delay locking block 100 includes a clock buffering sector 106.
The first phase delay sector 102 outputs the first delay clock RISING_CLK by delaying a first clock CLK_IN_R corresponding to the first clock edge of the source clock REF_CLK as much as a time determined by comparing phases of the source clock REF_CLK and a first feedback clock FEB_CLK1 to achieve the delay locking.
The second phase delay sector 104 outputs the second delay clock FALLING_CLK by delaying a second clock CLK_IN_F corresponding to the second clock edge of the source clock REF_CLK as much as a time determined by comparing phases of the source clock REF_CLK and a second feedback clock FEB_CLK2.
The first delay duplication modeling sector 103 outputs the first feedback clock FEB_CLK1 by reflecting a practical delay condition of the first clock CLK_IN_R to the delay locked loop clock DLL_CLK_USE.
The second delay duplication modeling sector 105 outputs the second feedback clock FEB_CLK2 by reflecting a practical delay condition of the second clock CLK_IN_F to a dummy delay locked loop DLL_CLK_DUMMY.
The clock buffering sector 106 outputs the source clock REF_CLK and the first and second clocks CLK_IN_R and CLK_IN_F by buffering the external clock CLK, CLKB inputted thereto from the external.
Herein, the first phase delay sector 102 among the components of the delay locking block 100 includes a first phase comparing unit 1022 for generating a first delay control signal DELAY_CON1 by comparing the phases of the source clock REF_CLK and the first feedback clock FEB_CLK1 and a first delay line 1024 for outputting the first delay clock RISING_CLK by delaying the first clock CLK_IN_R as much as a time determined corresponding to the first delay control signal DELAY_CON1.
The second phase delay sector 104 among the components of the delay locking block 100 includes a second phase comparing unit 1042 for generating a second delay control signal DELAY_CON2 by comparing the phases of the source clock REF_CLK and the second feedback clock FEB_CLK2 and a second delay line 1044 for outputting the second delay clock FALLING_CLK by delaying the second clock CLK_IN_F as much as a time determined corresponding to the second delay control signal DELAY_CON2.
Hereinafter, an operation of the conventional DLL circuit will be described with reference to the construction thereof.
An operation of the delay locking block 100 of the conventional semiconductor memory device may be classified into ‘an operation of before delay locked’ and ‘an operation of after delay locked’. As described above, a difference between the two classified operations is whether or not phases of the first and second delay clocks RISING_CLK and FALLING_CLK outputted from the delay locking block 100 are within a predetermined range. That is, if the phases of the first and second delay clocks RISING_CLK and FALLING_CLK are not within the predetermined range, it means that the delay locking is not achieved and this may be called ‘before delay locked’. On the other hand, if the phases of the first and second delay clocks RISING_CLK and FALLING_CLK are within the predetermined range, it means that the delay locking is achieved and this may be called ‘after delay locked’.
In particular, since all of the source clock REF_CLK and the first and second clocks CLK_IN_R and CLK_IN_F are generated by buffering the external clock CLK, CLKB, all of the source clock REF_CLK and the first and second clocks CLK_IN_R and CLK_IN_F are identical at a point in time where the DLL circuit of the semiconductor memory device starts to operate in a state of ‘before delay locked’.
But, since the first and second clocks CLK_IN_R and CLK_IN_F are delayed as much as predetermined initial delay times by passing through the first and second delay lines 1024 and 1044, respectively, and controlled and outputted to have phases contrary to each other, there occurs a phase difference between the source clock REF_CLK and the first and second delay clocks RISING_CLK and FALLING_CLK.
That is, the first delay clock RISING_CLK has a rising edge after a time corresponding to its initial delay time is passed from a point in time corresponding to a first edge, e.g., a rising edge, of the source clock REF_CLK and the second delay clock FALLING_CLK has a rising edge after a time corresponding to its initial delay time is passed from a point in time corresponding to a second edge, e.g., a falling edge, of the source clock REF_CLK.
After then, the first delay clock RISING_CLK is delayed as much as a time preset in the first delay duplication modeling sector 103 and outputted as the DLL circuit of the semiconductor memory device starts to operate. At this time, the time preset in the first delay duplication modeling sector 103 is identical to a delay time generated as the first clock CLK_IN_R passes through internal components of the semiconductor memory device such as control circuits, peripheral circuits, a cell array an so on.
Likewise, the second delay clock FALLING_CLK is delayed as much as a time preset in the second delay duplication modeling sector 105 and outputted. At this time, the time of delaying the first delay clock RISING_CLK in the first delay duplication modeling sector 103 is the same as the time of delaying the second delay clock FALLING_CLK in the second delay duplication modeling sector 105. That is, the delay time generated as the first clock CLK_IN_R passes through the internal components of the semiconductor memory device is identical to that generated as the second clock CLK_IN_F passes through internal components of the semiconductor memory device.
In the meantime, as shown in FIG. 1, it is noticed that the first and second delay duplication modeling sectors 103 and 105 are provided with not the first and second delay clocks RISING_CLK and FALLING_CLK but the delay locked loop clock DLL_CLK_USE and the dummy delay locked loop clock DLL_CLK_DUMMY outputted from the phase mixing block 140, respectively. This is because the phase mixing block 140 is a component operating only in a state of ‘after delay locked’ without operating in the state of ‘before delay locked’.
Namely, the phase mixing block 140 operates as a bypass of outputting signals inputted thereto themselves in the state of ‘before delay locked’ and finally performs a phase mixing operation for the input signals in the state of ‘after delay locked’.
Therefore, in the state of ‘before delay locked’, the first and second delay clocks RISING_CLK and FALLING_CLK inputted to the phase mixing block 140 may be the same as the delay locked loop clock DLL_CLK_USE and the dummy delay locked loop clock DLL_CLK_DUMMY outputted from the phase mixing block 140, respectively.
The conventional DLL circuit of the semiconductor memory device operates to change clocks in the state of ‘before delay locked’ having states described above as follows until the state of ‘before delay locked’ is terminated.
First of all, the rising edge of the first delay clock RISING_CLK outputted from the first delay line 1024 is delay-locked with the rising edge of the reference clock REF_CLK by further delaying the first clock CLK_IN_R, which is used to be delayed by its initial delay time, as much as a first predetermined time through appropriately controlling the first delay line 1024.
At the same time, the rising edge of the second delay clock FALLING_CLK outputted from the second delay line 1044 is delay-locked with the rising edge of the reference clock REF_CLK by further delaying the second clock CLK_IN_F, which is used to be delayed by its initial delay time, as much as a second predetermined time through appropriately controlling the second delay line 1044.
Herein, a delay amount of the first delay line 1024 delaying the first clock CLK_IN_R is different from that of the second delay line 1044 delaying the second clock CLK_IN_F. That is, the first predetermined time is different from the second predetermined time.
As described above, if the first delay locking signal LOCK_STATE_R is enabled as the rising edge of the first delay clock RISING_CLK is synchronized with the rising edge of the reference clock REF_CLK and the second delay locking signal LOCK_STATE_F is enabled as the rising edge of the second delay clock FALLING_CLK is synchronized with the rising edge of the reference clock REF_CLK, the delay locking enable signal DCC_EN is enabled and thus the state of ‘before delay locked’ is terminated.
Then, the semiconductor memory device operates as the state of ‘after delay locked’. At this time, the phase mixing block 140 among the components of the DLL circuit does not operate as the bypass and performs the operation of mixing the phases of the first and second delay clocks RISING_CLK and FALLING_CLK. As a result, a duty ratio of the delay locked loop clock DLL_CLK_USE outputted from the phase mixing block 140 is corrected to 50:50.
Referring back to the reason why the aforementioned DLL circuit exists, the DLL circuit is required to synchronize the phase of the internal clock with that of the external clock by conversely compensating the delay time of the phase of the internal clock occurring by the operation of the semiconductor memory device.
That is, if the state of ‘before delay locked’ is terminated, the delay locked loop clocks DLL_CLK_USE and DLL_CLK_DUMMY and the reference clock REF_CLK are in a state of their rising edges being synchronized with each other, wherein the delay locked loop clocks DLL_CLK_USE and DLL_CLK_DUMMY are the same as the first and second delay clocks RISING_CLK and FALLING_CLK at the point in time where the state of ‘before delay locked’ is terminated and the reference clock REF_CLK is the external clock. Therefore, practically, the operation of the DLL circuit should be terminated at the same time of the termination of the state of ‘before delay locked’.
A recent semiconductor memory device tends to output more than two data during one period of an internal clock while an early semiconductor memory device outputs one data during one period of the internal clock.
For instance, a semiconductor memory device, which outputs one data at a rising edge of the delay locked loop clock DLL_CLK_USE and one data at a falling edge thereof, such as a DDR SDRAM device, a DDR2 SDRAM device, a DDR3 SDRAM device and so on has been developed.
At this time, if a logic high period from a point in time where the rising edge of the internal clock occurs to a point in time where the falling edge thereof occurs is relatively long and a logic low period from a point in time where the falling edge of the internal clock occurs to a point in time where the rising edge thereof occurs is relatively short, a sufficient time is provided to a data input/output operation during the logic high period but a sufficient time is not provided to a data input/output operation during the logic low period, so that there may occur a failure in the data input/output operation.
Therefore, an operation of correcting a duty ratio of the delay locked loop clock DLL_CLK_USE should be performed at an ending part of the DLL circuit.
Referring to a detailed operation of the phase mixing block 140 in the state of ‘after delay locked’, a logic high period of the first delay clock RISING_CLK is consistent with a logic high period of the reference clock REF_CLK and a logic high period of the second delay clock FALLING_CLK is consistent with to a logic low period of the reference clock REF_CLK. Further, since the phases of the first delay clock RISING_CLK and the second delay clock FALLING_CLK are in the synchronized state in the state of ‘before delay locked’, the phase detecting block 120 performs an operation of generating the weight control signal WR_SEL by comparing a falling edge point of the first delay clock RISING_CLK with a falling edge point of the second delay clock FALLING_CLK.
Then, the mixing control sector 142 properly controls a value of the mixing control signal CTRL to make the DCC phase mixing sector 144 mix the phases of the first and second delay clocks RISING_CLK and FALLING_CLK with a weight corresponding to the weight control signal WR_SEL.
Through the above processes, the DCC phase mixing sector 144 generates the delay locked loop clock DLL_CLK_USE having a duty ratio of 50:50.
After then, the phase split block 110A generates the first split clock RCLKDLL corresponding to a first edge, e.g., a rising edge, of the delay locked loop clock DLL_CLK_USE and the second split clock FCLKDLL corresponding to a second edge, e.g., a falling edge, of the delay locked loop clock DLL_CLK_USE by splitting the delay locked loop clock DLL_CLK_USE whose duty ratio is corrected to 50:50.
At this time, the dummy DCC phase mixing sector 145 and the dummy phase split block 110B are not required to operate since they are only used to bypass the first and second delay clocks RISING_CLK and FALLING_CLK inputted to the phase mixing block 140 in the state of ‘before delay locked’ in the same transmission environment as in the DCC phase mixing sector 144 and the phase split block 110A by becoming a load having a resistance value corresponding to a resistance value which the components constructing the DCC phase mixing sector 144 and the phase split block 110A have. Therefore, the dummy DCC phase mixing sector 145 and the dummy phase split block 110B only perform the bypass operation in the state of ‘before delay locked’ and they do not perform any operation in the state of ‘after delay locked’.
Through the above described the operation of ‘before delay locked’ and the operation of ‘after delay locked’ of the DLL circuit, the delay locked loop clock DLL_CLK_USE achieving two objects described below is generated.
Since the first object is to conversely compensate the internal clock to allow data outputted from the semiconductor memory device to be synchronized with the external clock, it is achieved in the state of ‘before delay locked’ of the DLL circuit.
Meanwhile, since the second object is to output data at the first edge of the internal clock as well as at the second edge thereof by exactly correcting the duty ratio of the internal clock to 50:50, it is achieved in the state of ‘after delay locked’ of the DLL circuit.
In order to accomplish the two objects, the conventional DLL circuit described in FIG. 1 employs a dual loop scheme. The main reason using the dual loop scheme is to exactly correct the duty ratio of the internal clock to 50:50, which is the second object of the two objects.
Namely, while the first object that is to conversely compensate the internal clock can be easily accomplished by using a DLL circuit employing a single loop scheme, the second object, i.e., making the duty ratio of the internal clock have exactly 50:50, cannot be easily accomplished by using the DLL circuit employing the single loop scheme. Although the second object is achieved using the DLL circuit employing the single loop scheme, its accuracy may be substantially lower than that of the DLL circuit employing the dual loop scheme.
Thus, the DLL circuit using the dual loop scheme has been usually used in the semiconductor memory device.
In the DLL circuit employing the dual loop scheme, the phase mixing block 140 performs the operation of mixing the phases of the first delay clock RISING_CLK and the second delay clock FALLING_CLK in the state of ‘after delay locked’ as described above to make the duty ratio of the internal clock to exactly 50:50, which is the second object.
However, a period where the phase mixing operation of the phase mixing block 140 is exactly required in the state of ‘after delay locked’ is only a period where a data read operation is performed to practically output data. Therefore, although the phase mixing block 140 does not operate in an idle state where any operation including the data read operation is not performed or in a power down mode, it does not affect on the operation of the semiconductor memory device.
Nevertheless, since the phase mixing block 140 continuously performs the phase mixing operation in the state of ‘after delay locked’ in the conventional DLL circuit employing the dual loop scheme, unnecessary current consumption occurs.
For the reference, the biggest difference between the DLL circuit employing the dual loop scheme and the DLL circuit employing the single loop scheme is that the DLL circuit employing the single loop scheme uses one internal clock while the DLL circuit employing the dual loop scheme uses two internal clocks when delay-locking the internal clock and the external clock. This is well known in the art and therefore detailed explanation thereof is omitted.